Conventionally, after grinding, cleaning and etching steps on a semiconductor wafer sliced from a single crystal, the surface of the semiconductor wafers is smoothed by polishing.
In the case of single-side polishing (or SSP for short), semiconductor wafers are held during processing on the rear side on a support plate using cement, by means of vacuum or by means of adhesion and are subjected to polishing on the other side.
In the case of double-side polishing (DSP), semiconductor wafers are introduced loosely into a thin carrier and are polished on the front and rear sides simultaneously in a manner “floating freely” between an upper and a lower polishing plate respectively covered with a polishing pad. This polishing method is effected with supply of a polishing agent slurry, normally generally on the basis of a silica sol. In the case of DSP, the front and rear sides of the semiconductor wafer are simultaneously polished at the same time.
A suitable double-side polishing machine is disclosed in DE 100 07 390 A1.
Polishing methods also include so-called polishing using fixedly bonded abrasives (“Fixed Abrasive Polishing”, FAP), in which the semiconductor wafer is polished on a polishing pad which, in contrast to DSP or CMP polishing pads, contains an abrasive material bonded in the polishing pad (“Fixed Abrasive” or FA pad). The addition of a polishing agent slurry as in the case of DSP can be dispensed with, in principle, in the case of FAP.
The German Patent Application DE 102 007 035 266 A1 describes for example a method for polishing a substrate composed of silicon material, comprising two polishing steps using FA pads, which differ in that, in one polishing step, a polishing agent slurry containing non-bonded abrasive material as solid material is introduced between the substrate and the polishing pad, while in the second polishing step the polishing agent slurry is replaced by a polishing agent solution that is free of solid materials.
Following DSP or FAP, the front sides of the semiconductor wafers are generally polished in haze-free fashion. This is effected using a softer polishing pad with the aid of an alkaline polishing sol. This step is often referred to as CMP polishing in the literature. CMP methods are disclosed for example in US 2002-0077039 and also in US 2008-0305722.
In the case of DSP, the semiconductor wafers are situated in carriers which are usually thinner than the semiconductor wafers. DE 199 05 737 A1 claims a double-side polishing method in which the initial thickness of the semiconductor wafer is 20 to 200 μm greater than the carrier thickness. This is referred to as polishing the semiconductor wafer with an “overhang”. The carriers during double-side polishing usually have a thickness of 400 to 1200 μm.
Usually, the polishing pad situated on the lower polishing plate is in contact with the front side of the semiconductor wafer to be polished, while the rear side of the semiconductor wafer touches the polishing pad situated on the upper polishing plate.
DE 100 04 578 C1 describes the use of different polishing pads for the upper and lower polishing plates. The polishing pad adhering to the upper polishing plate is pervaded with a network of channels, while the polishing pad adhering to the lower polishing plate does not have such texturing, but rather a smooth surface.
An improved distribution of the polishing agent used is achieved as a result of the texturing of the upper polishing pad. The supply of polishing agent is usually effected from the top toward the bottom. The polishing agent therefore flows through the channels of the upper polishing pad and then from the upper polishing pad through cutouts or openings in the carrier to the lower polishing pad or to the front side of the semiconductor wafer.
Moreover, the channels of the upper polishing pad prevent the rear side of the semiconductor wafer from adhering to the upper polishing pad. In accordance with DE 100 04 578 C1, the upper polishing pad comprises a regular checkered arrangement of channels having a segment size of 5 mm×5 mm to 50 mm×50 mm and a channel width and depth of 0.5 to 2 mm. With this arrangement, polishing is effected under a polishing pressure preferably of 0.1 to 0.3 bar.
However, a procedure in accordance with DE 100 04 578 C1 results in an asymmetrical polishing removal at the outer edge of the semiconductor wafer at the opposite sides (rear side and front side).
It has been found that a so-called edge roll-off (edge decrease with regard to the thicknesses) results, which is more pronounced at the front side of the semiconductor wafer than on the rear side.